onbreak {resume}
transcript on

set PrefMain(saveLines) 50000
.main clear

if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

# load designs

# insert files specific to your design here

vlog -sv -work rtl_work +define+SIMULATION SRAM_Controller.v
vlog -sv -work rtl_work tb_SRAM_Emulator.v
vlog -sv -work rtl_work Clock_100_PLL.v
vlog -sv -work rtl_work DP_RAM0.v
vlog -sv -work rtl_work DP_RAM1.v
vlog -sv -work rtl_work IDCT.v
vlog -sv -work rtl_work Mul32.v
vlog -sv -work rtl_work SCalc.v
vlog -sv -work rtl_work SPLoad.v
vlog -sv -work rtl_work SWrite.v
vlog -sv -work rtl_work tb_IDCT.v
vlog -sv -work rtl_work TCalc.v

# specify library for simulation
vsim -t 100ps -L altera_mf_ver -lib rtl_work tb_IDCT

# Clear previous simulation
restart -f

view wave
add wave Clock_50
######################################################
# IDCT
######################################################
add wave uut/resetn
add wave uut/start
add wave uut/state
add wave uut/finish

# SRAM
add wave -hexadecimal uut/SRAM_Addr
add wave -hexadecimal uut/SRAM_Read
add wave -hexadecimal uut/SRAM_Write
add wave uut/SRAM_we

# Offsets
add wave -hexadecimal uut/preIDCToffset
add wave -unsigned uut/preIDCTrow
add wave -unsigned uut/preIDCTcol
add wave -hexadecimal uut/yuvOffset
add wave -unsigned uut/yuvRow
add wave -unsigned uut/yuvCol
add wave uut/preIDCTYDone
add wave uut/yDone

# Submodule start and finish
# spLoader
add wave uut/spLoader0Start
add wave uut/spLoader0Finish
add wave uut/spLoader1Start
add wave uut/spLoader1Finish
# sWriter
add wave uut/sWriter0Start
add wave uut/sWriter0Finish
add wave uut/sWriter1Start
add wave uut/sWriter1Finish
# tCalc
add wave uut/tCalc0Start
add wave uut/tCalc0Finish
#add wave uut/tCalc1Start
#add wave uut/tCalc1Finish
# sCalc
add wave uut/sCalc0Start
add wave uut/sCalc0Finish
#add wave uut/sCalc1Start
#add wave uut/sCalc1Finish

# spLoader0 submodule signals
#add wave uut/spLoader0/state
#add wave -hexadecimal uut/spLoader0/SRAM_Addr
#add wave -hexadecimal uut/spLoader0/baseOffset
#add wave -unsigned uut/spLoader0/col
#add wave uut/spLoader0/DP_we

# spLoader1 submodule signals
#add wave uut/spLoader1/state
#add wave -hexadecimal uut/spLoader1/SRAM_Addr
#add wave -hexadecimal uut/spLoader1/baseOffset
#add wave -unsigned uut/spLoader0/col

# sWriter0 submodule signals
#add wave uut/sWriter0/state
#add wave -hexadecimal uut/sWriter0/DP_ReadClipped
#add wave -hexadecimal uut/sWriter0/DP_Read

# sWriter1 submodule signals
#add wave uut/sWriter1/state
#add wave -hexadecimal uut/sWriter1/DP_ReadClipped
#add wave -hexadecimal uut/sWriter1/DP_Read

# tCalc0 submodule signals
add wave uut/tCalc0/state
add wave -unsigned uut/tCalc0/DP0_Addr0
add wave -hexadecimal uut/tCalc0/DP0_Read0
add wave -unsigned uut/tCalc0/DP0_Addr1
add wave -hexadecimal uut/tCalc0/DP0_Read1
add wave -unsigned uut/tCalc0/DP1_Addr0
add wave -hexadecimal uut/tCalc0/DP1_Write0
add wave uut/tCalc0/DP1_we0

# sCalc0 submodule signals
#add wave uut/sCalc0/state
#add wave -unsigned uut/sCalc0/DP0_Addr1
#add wave -hexadecimal uut/sCalc0/DP0_Read1
#add wave -unsigned uut/sCalc0/DP1_Addr0
#add wave -hexadecimal uut/sCalc0/DP1_Read0
#add wave -unsigned uut/sCalc0/DP1_Addr1
#add wave -hexadecimal uut/sCalc0/DP1_Write1
#add wave uut/sCalc0/DP1_we1

# sCalc1 submodule signals
#add wave uut/sCalc1/state
#add wave -unsigned uut/sCalc1/DP0_Addr1
#add wave -hexadecimal uut/sCalc1/DP0_Read1
#add wave -unsigned uut/sCalc1/DP1_Addr0
#add wave -hexadecimal uut/sCalc1/DP1_Read0
#add wave -unsigned uut/sCalc1/DP1_Addr1
#add wave -hexadecimal uut/sCalc1/DP1_Write1
#add wave uut/sCalc1/DP1_we1

# run complete simulation
run -all

destroy .structure
destroy .signals
destroy .source

simstats
